VHDL Training

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VHDL training is an essential course for taking a jumpstart in VLSI design domain. VHDL stands for VHSIC Hardware Description Language where VHSIC can be further expanded to Very High Speed Integrated Circuit. VHDL is widely used in electronic design automation.

This comprehensive course commences by introducing VLSI (Very Large Scale Integration). Advance digital design concepts are delivered to build the foundation for understanding VHDL language. The course explains the use of VHDL language in logic design and its code structure. Participants gain the understanding and building skills of VHDL constructs that can be synthesized into programmable logic device hardware. The learning curve encompasses ModelSIM and Xilinx.

Upon the completion of training, you will be proficient in the following skillset:

  • Understanding the concept of VLSI
  • Learn the basic building blocks for advanced digital design
  • Learn about VHDL and different design levels
  • Distinguish coding between primitive, data flow, behavioral and structural programming
  • Explore state machine and machine designing
  • Manage designs using ModelSIM and Xilinx
  • Process of synthesis of VHDL
Target audience
  • Final year engineering and IT graduate students
  • Professionals switching to VLSI design domain
Prerequisites

Candidates having background of digital system designing and any programming language experience can undergo this training.

Module 1: Introduction to VLSI

Module 2: Advanced Digital Design

Combination Device

  • Adders
  • Subtractor
  • Mux/Demux
  • Encoder/Decoder
  • Parity checker/generator

Sequential Device

  • Flip Flops
  • Latchs
  • Register Application
    • Shifters
    • Counters
  • Memory
    • RAM
    • SRAM
    • ROM

Logic Implementation

  • Using FSM
  • Logic Mapping

Module 3: VHDL

Introduction HDL's

  • Introduction to HDL's (VHDL)
  • Introduction to Design Levels

Code Structure

  •  Fundamental VHDL units
  •  LIBRARY Declaration
  •  Entity Declaration
  •  Architecture Declaration

Data Types

  • Pre-defined Data Types
  • User Defined Data Type
  • Data Conversion

Operator & attributes

  •   Operators
  •    Attributes ,User Defined attributes
  •    Generic
  •    Operator Overloading

Primitive Programming

  • Introduction to Primitive Programming
  • Primitives List
  • Use of Primitive
  • Signal Declaration and use of Signal

Data Flow Programming

  • Introduction to Data Flow Programming
  • Use of Operators
  • When Statements, Data Flow designing

Behavioral Programming

  • Introduction to Behavioral Programming
  • Process
  • Signals and variables
  • Wait statements
  • Case Statement

Signals & Variables

State Machine designing

Memory Designing

  • RAM Designing
  • ROM Designing

Structural Programming

  • Component
  • Port map
  • Interface method

Function & Procedure

Advanced Topic in VHDL

  • Package Declaration
  • Introduction to assert ,Configuration

Verification

  • Delay Model
  • Test Bench

Looping

Module 4: Synthesis of VHDL

Module 5: Project Software Package

  • ModelSIM
  • Xilinx

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