ASIC Design and Verification Training

  • Overview
  • Course Content
  • Drop us a Query

ASIC Design and Verification training empowers the participants to contribute to ASIC (application-specific integrated circuit) industry. ASIC is designed for a specific application rather than going for general purpose designing. This designing supports the development of embedded systems.


The curriculum is designed to impart the knowledge and skills for RTL (Register Transfer Level) designing and netlist generation. Participants practice static time analysis (STA) for ASIC design verification and validating the timing performance of the design. The learning curve encompasses SOC designing and also focuses on HDL techniques for high performance designs intended for programmable logic devices.

Upon the completion of the raining you will be able to:

  • Understand the fundamentals of logic designing and Analog/Mixed signal (AMS) IC designing
  • Use Verilog, Linux, Tcl
  • Develop advanced RTL design using Verilog
  • Perform ASIC verification
  • Conduct analysis of backend design parameter
  • Conduct design Synthesis for ASIC methodologies
  • Demonstrate high performance designs using HDL techniques
Target audience
  • Final year students of electronics engineering courses
  • Processionals from VLSI domain
  • Professionals aspire to change their job profile from backend to front end
  • Professionals willing to switch the domain
Prerequisites

Candidates having knowledge of digital design logic and system architecture are the ideal participants for this course.

Fundamentals of AMS IC Design

  • Fundamentals of Analog Circuit Design
  • Fundamentals of Logic Design
  • Designing using Verilog, Linux & Tcl
  • ASIC Design Flow

ASIC Design Flow

  • RTL Designing
  • Constraints Designing

Netlist Generation

ASIC verification

  • STA analysis
  • Essential Level DFT

Backend Design Flow of ASIC

Analysis of Backend Design parameter

Essential Level SOC designing

Digital Subsystem Design and Verification

  • Advanced RTL Design using Verilog
  • RTL Verification using Verilog

Implementation and Timing Closure of Digital IC’s

  • Design Synthesis for ASIC methodologies
  • Full custom
  • Automatic Place and Route concepts for Functional blocks
  • Full chip IC’s for various package types and IR drop specs

Designing for programmable VLSI systems Live Project

  • Programmable VLSI architectures
  • HDL techniques for high performance designs intended for programmable logic devices
  • Optimization and timing analysis techniques

A Few Things You'll Love!

What our Students Speak

+