CMOS & FPGA Design Flow Training

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CMOS & FPGA Design Flow Training lays emphasis on the designing, synthesis, implementation, and verification. The curriculum is designed to impart knowledge and skills on the use of tools and techniques used throughout the FPGA (Field-Programmable Gate Array) design cycle. Participants will learn RTL for designing; System Verilog and Xilinx for synthesis and implementation of HDL designs. For the verification purpose, the hands-on exposure on ModelSIM, QuestSIM, and Xilinx ISE is provided. The training collectively bestows to deliver a view point and approaches used in the industry for solving design problems.

Upon the completion of the training, you will be proficient in the following skills:

  • Differentiate among different technologies say NMOS, PMOS, CMOS
  • Understand the details of CMOS
  • Design exercise using CMOS
  • Fabrication flows and fundamentals
  • Architectures of XILINX, ALTERA Devices
  • Architecture based coding and constraints based synthesis
  • Use industry standard tools
Target audience
  • Final year students of electronics engineering courses
  • Processionals from VLSI domain
  • Professionals aspire to change their job profile from frontend to backend
  • Professionals willing to switch the domain

Candidates having knowledge of Register-Transfer Level (RTL) are the ideal participants for this course.

Module 1: Introduction to VLSI Module 2: CMOS

Module 2: CMOS

  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for NMOS/PMOS/CMOS
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals

Module 3: FPGA Flow

  • Re-configurable Devices, FPGA’s/CPLD’s
  • Architectures of XILINX, ALTERA Devices
  • Designing with FPGAs
  • FPGA’s and its Design Flows
  • Architecture based coding
  • Efficient resource utilization
  • Constrains based synthesis
  • False paths and multi cycle paths
  • UCF file creation
  • Timing analysis/Floor Planning
  • Place and route/RPM
  • Back annotation, Gate level simulation, SDF Format
  • DSP on FPGA
  • Writing Scripts
  • Hands on experience with industry Standard Tools
  • ASIC Flow

Module 4: Project Software Package

  • Xilinx ISE

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